View HCPL-5201_6727025.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? ? ? ? ? dual marked with device part number and dscc standard microcircuit drawing ? ? ? ? ? manufactured and tested on a mil-prf-38534 certified line ? ? ? ? ? qml-38534, class h and k ? ? ? ? ? four hermetically sealed package configurations ? ? ? ? ? performance guaranteed over -55c to +125c ? ? ? ? ? wide v cc range (4.5 to 20 v) ? ? ? ? ? 350 ns maximum propagation delay ? ? ? ? ? cmr: > 10,000 v/ s typical ? ? ? ? ? 1500 vdc withstand test voltage ? ? ? ? ? three state output available ? ? ? ? ? high radiation immunity ? ? ? ? ? hcpl-2200/31 function compatibility ? ? ? ? ? reliability data available ? ? ? ? ? compatible with lsttl, ttl, and cmos logic description these units are single, dual and quad channel, hermetically sealed optocouplers. the products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full mil-prf-38534 class level h or k testing or from the appropriate dscc drawing. all devices are manufactured and tested on a mil-prf- 38534 certified line and are included in the dscc qualified manufacturers list qml-38534 for hybrid microcircuits. each channel contains an algaas light emitting diode which is optically coupled to an integrated high gain photon detector. the detector has a threshold with hysteresis which provides differential mode noise immunity and eliminates the potential for output signal chatter. the detector in the single channel units has a tri- state output stage which allows for direct connection to data buses. the output is noninverting. the detector ic has an internal shield that provides a guaranteed common mode transient immunity of up to 10,000 v/ s. improved power supply rejection eliminates the need for special power supply bypass precautions. applications ? ? ? ? ? military and space ? ? ? ? ? high reliability systems ? ? ? ? ? transportation and life critical systems ? ? ? ? ? high speed line receiver ? ? ? ? ? isolated bus driver (single channel) ? ? ? ? ? pulse transformer replacement ? ? ? ? ? ground loop elimination ? ? ? ? ? harsh industrial environments ? ? ? ? ? computer-peripheral interfaces a 0.1 mf bypass capacitor must be connected between v cc and gnd pins. agilent hcpl-520x, hcpl-523x, hcpl-623x, hcpl-625x, 5962-88768, 5962-88769 hermetically sealed low if, wide vcc, logic gate optocouplers data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd.
2 package styles for these parts are 8 pin dip through hole (case outline p), 16 pin dip flat pack (case outline f), and leadless ceramic chip carrier (case outline 2). devices may be purchased with a variety of lead bend and plating options, see selection guide table for details. standard microcircuit drawing (smd) parts are available for each package and lead style. truth tables (positive logic) multichannel devices functional diagram multiple channel devices available multichannel devices input output on (h) h off (l) l single channel devices input enable output on (h) h z off (l) h z on (h) l h off (l) l l v cc v o v e gnd because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are identical for all parts. occasional exceptions exist due to package variations and limitations and are as noted. additionally, the same package assembly processes and materials are used in all devices. these similarities give justification for the use of data obtained from one part to represent other parts performance for die related reliability and certain limited radiation test results. 8 pin dip 8 pin dip 16 pin flat pack 20 pad lccc through hole through hole unformed leads surface mount 1 channel 2 channels 4 channels 2 channels functional diagrams v cc 7 5 6 8 v o v e gnd 1 2 3 4 5 7 6 8 12 10 11 9 gnd v o4 v o3 1 3 2 4 16 14 15 13 v cc v o2 v o1 gnd 1 v o2 19 20 2 3 v o1 8 7 v cc2 v cc1 10 gnd 2 15 13 12 v cc 7 5 6 8 v o1 gnd 1 2 3 4 v o2 note: multichannel dip and flat pack devices have common v cc and ground. single channel dip has an enable pin 6. lccc (leadless ceramic chip carrier) package has isolated channels with separate v cc and ground connections.
3 selection guide?package styles and lead configuration options package 8 pin dip 8 pin dip 16 pin flat pack 20 pad lccc lead style through hole through hole unformed leads surface mount channels 1 2 4 2 common channel wiring none v cc gnd v cc gnd none agilent part number and options commercial hcpl-5200 hcpl-5230 hcpl-6250 hcpl-6230 mil-prf-38534 class h HCPL-5201 hcpl-5231 hcpl-6251 hcpl-6231 mil-prf-38534 class k hcpl-520k hcpl-523k hcpl-625k hcpl-623k standard lead finish gold plate gold plate gold plate solder pads solder dipped* option 200 option 200 butt joint/gold plate option 100 option 100 gull wing/soldered* option 300 option 300 class h smd part number prescript for all below 5962- 5962- 5962- 5962- either gold or soldered 8876801px 8876901px 8876903fx 88769022x gold plate 8876801pc 8876901pc 8876903fc solder dipped* 8876801pa 8876901pa 88769022a butt joint/gold plate 8876801yc 8876901yc butt joint/soldered* 8876801ya 8876901ya gull wing/soldered* 8876801xa 8876901xa class k smd part number prescript for all below 5962- 5962- 5962- 5962- either gold or soldered 8876802kpx 8876904kpx 8876906kfx 8876905k2x gold plate 8876802kpc 8876904kpc 8876906kfc solder dipped* 8876802kpa 8876904kpa 8876905k2a butt joint/gold plate 8876802kyc 8876904kyc butt joint/soldered* 8876802kya 8876904kya gull wing/soldered* 8876802kxa 8876904kxa * solder contains lead
4 outline drawings 8 pin dip through hole, 1 and 2 channel 8.13 (0.320) max. 5.23 (0.206) max. 2.29 (0.090) max. 7.24 (0.285) 6.99 (0.275) 1.27 (0.050) ref. 0.46 (0.018) 0.36 (0.014) 11.13 (0.438) 10.72 (0.422) 2.85 (0.112) max. 0.89 (0.035) 0.69 (0.027) 0.31 (0.012) 0.23 (0.009) 0.88 (0.0345) min. 9.02 (0.355) 8.76 (0.345) note: dimensions in millimeters (inches). 3.81 (0.150) min. 4.32 (0.170) max. 9.40 (0.370) 9.91 (0.390) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) note: dimensions in millimeters (inches). 16 pin flat pack, 4 channels
5 20 terminal lccc surface mount, 2 channels 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 1.02 (0.040) (3 plcs) 4.95 (0.195) 5.21 (0.205) 8.70 (0.342) 9.10 (0.358) 1.78 (0.070) 2.03 (0.080) 0.51 (0.020) 0.64 (0.025) (20 plcs) 1.52 (0.060) 2.03 (0.080) metalized castillations (20 plcs) 2.16 (0.085) terminal 1 identifier note: dimensions in millimeters (inches). solder thickness 0.127 (0.005) max. 1.14 (0.045) 1.40 (0.055) leaded device marking leadless device marking *qualified parts only compliance indicator,* date code, suffix (if needed) a qyywwz xxxxxx xxxxxxx xxx xxx 50434 country of mfr. agilent fscn* dscc smd* pin one/ esd ident agilent p/n dscc smd* agilent designator *qualified parts only compliance indicator,* date code, suffix (if needed) a qyywwz xxxxxx xxxx xxxxxx xxx 50434 dscc smd* agilent fscn* agilent designator country of mfr. agilent p/n pin one/ esd ident dscc smd*
6 hermetic optocoupler options option description 100 surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. this option is available on commercial and hi-rel product in 8 pin dip (see drawings below for details). 200 lead finish is solder dipped rather than gold plated. this option is available on commercial and hi-rel product in 8 pin dip. dscc drawing part numbers contain provisions for lead finish. all leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. 300 surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. this option is available on commercial and hi-rel product in 8 pin dip (see drawings below for details). this option has solder dipped leads. 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 0.20 (0.008) 0.33 (0.013) 0.51 (0.020) min. 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 9.65 (0.380) 9.91 (0.390) 5? max. 4.57 (0.180) max. note: dimensions in millimeters (inches).
7 absolute maximum ratings recommended operating conditions esd classification 8 pin ceramic dip single channel schematic parameter symbol min. max. units storage temperature range t s -65 +150 c operating ambient temperature t a -55 +125 c junction temperature t j +175 c case temperature t c +170 c lead solder temperature (1.6 mm below seating plane) 260 for 10 s c average forward current, each channel i f avg 8ma peak input current, each channel i fpk 20 [1] ma reverse input voltage, each channel v r 3v average output current, each channel i o 15 ma supply voltage v cc 0.0 20 v output voltage, each channel v o -0.3 20 v package power dissipation, each channel p d 200 mw single channel product only tri-state enable voltage v e -0.3 20 v (mil-std-883, method 3015) hcpl-5200/01/0k and hcpl-6230/31/3k ( ? ), class 1 hcpl-5230/31/3k and hcpl-6250/51/5k (dot), class 3 parameter symbol min. max. units power supply voltage v cc 4.5 20 v input current, high level, each channel i fh 28ma input voltage, low level, each channel v fl 00.8v fan out (ttl load), each channel n 4 single channel product only high level enable voltage v eh 2.0 20 v low level enable voltage v el 00.8v note enable pin 6. an external 0.01 f to 0.1 f bypass capacitor is recommended between v cc and ground for each package type.
8 electrical characteristics t a = -55c to +125c, 4.5 v v cc 20 v, 2 ma i f(on) 8 ma, 0 v v f(off) 0.8 v, unless otherwise specified. parameter symbol group a, sub-groups [11] test conditions limits units fig. notes min. typ.* max. logic low output voltage v ol 1, 2, 3 i ol = 6.4 ma (4 ttl loads) 0.5 v 1, 3 2 logic high output voltage v oh 1, 2, 3 i oh = -2.6 ma, (**v oh = v cc - 2.1 v) 2.4 ** v2, 3 2 na i oh = -0.32 ma 3.1 output leakage current (v out > v cc ) i ohh 1, 2, 3 v o = 5.5 v i f = 8 ma v cc = 4.5 v 100 a 2 v o = 20 v 500 logic low supply current single channel i ccl 1, 2, 3 v cc = 5.5 v v f = 0 v v e = don't care 4.5 6 ma v cc = 20 v 5.3 7.5 dual channel v cc = 5.5 v v f1 = v f2 = 0 v 9.0 12 v cc = 20 v 10.6 15 quad channel v cc = 5.5 v v f1 = v f2 = v f3 = v f4 =0 v 14 24 v cc = 20 v 17 30 logic high supply current single channel i cch 1, 2, 3 v cc = 5.5 v i f = 8ma v e = don't care 2.9 4.5 ma v cc = 20 v 3.3 6 dual channel v cc = 5.5 v i f1 = i f2 = 8ma 5.8 9 v cc = 20 v 6.6 12 quad channel v cc = 5.5 v i f1 = i f2 = i f3 = i f4 = 8ma 918 v cc = 20 v 11 24 logic low short circuit output current i osl 1, 2, 3 v o = v cc = 5.5 v v f = 0 v 20 ma 2, 3 v o = v cc = 20 v 35 logic high short circuit output current i osh 1, 2, 3 v cc = 5.5v i f = 8 ma v o = gnd -10 ma 2, 3 v cc = 20 v -25 input forward voltage v f 1, 2, 3 i f = 8 ma 1.0 1.3 1.8 v 4 2 input reverse breakdown voltage bv r 1, 2, 3 i r = 10 a3 v 2 input-output insulation leakage current i i-o 1 v i-o = 1500 vdc, t = 5s, rh 65%, t a = 25c 1.0 a 4, 5 logic high common mode transient immunity |cm h | 9, 10, 11 i f = 2 ma, v cm = 50 v p-p 1000 10,000 v/ s 9 2, 6, 12 logic low common mode transient immunity |cm l | 9, 10, 11 i f = 0 ma, v cm = 50 v p-p 1000 10,000 v/ s 9 2, 6, 12 propagation delay time to logic low t phl 9, 10, 11 173 350 ns 5, 6 2, 7 propagation delay time to logic high t plh 9, 10, 11 118 350 ns 5, 6 2, 7
9 electrical characteristics - single channel product only t a = -55c to +125c, 4.5 v v cc 20 v, 2 ma i f (on) 8 ma, 0 v v f(off) 0.8 v, 2.0 v v eh 20 v, 0 v v el 0.8 v, unless otherwise specified. *all typical values are at v cc = 5 v, t a = 25c, i f(on) = 5 ma unless otherwise specified. parameter symbol group a, sub-groups [11] test conditions limits units fig. notes min. typ.* max. hign impedance state utput current i ozl 1,2,3 v o = 0.4 v v en = 2 v, v f = 0 v -20 a i ozh 1,2,3 v o = 2.4 v v en = 2 v, i f = 8 ma 20 a v o = 5.5 v 100 v o = 20 v 500 logic high enable voltage v eh 1, 2, 3 2.0 v logic low enable voltage v el 1, 2, 3 0.8 v logic high enable current i eh 1, 2, 3 v en = 2.7 v 20 a v en = 5.5 v 100 v en = 20 v 0.004 250 logic low enable current i el 1, 2, 3 v en = 0.4 v -0.32 ma
10 notes: 1. peak forward input current pulse width < 50 s at 1 khz maximum repetition rate. 2. each channel of a multichannel device. 3. duration of output short circuit time not to exceed 10 ms. 4. all devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all outpu t leads or terminals shorted together. 5. this is a momentary withstand test, not an operating condition. 6. cm l is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (v o < 0.8 v). cm h is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (v o > 2.0 v). 7. t phl propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 v point on the leading edge of the output pulse. the t plh propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 v point on the trailing ed ge of the output pulse. 8. measured between each input pair shorted together and all output connections for that channel shorted together. 9. measured between adjacent input pairs shorted together for each multichannel device. 10. zero-bias capacitance measured between the led anode and cathode. 11. standard parts receive 100% testing at 25c (subgroups 1 and 9). smd, class h and class k parts receive 100% testing at 25, 125, and ?55c (subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 12. parameters are tested as part of device initial characterization and after design and process changes. parameters guaranteed to limits specified for all lots not specifically tested. typical characteristics all typical values are at t a = 25c, v cc = 5 v, i f(on) = 5 ma unless otherwise specified. parameter symbol test conditions typ. units fig. notes input current hysteresis i hys v cc = 5 v 0.07 ma 3 2 input diode temperature coefficient ? v f ? t a i f = 8 ma -1.25 mv/c 2 resistance (input-output) r i-o v i-o = 500 vdc 10 13 ? 2, 8 capacitance (input-output) c i-o f = 1 mhz 2.0 pf 2, 8 input capacitance c in v f = 0 v, f = 1 mhz 20 pf 2, 10 output rise time (10-90%) t r 45 ns 5, 7 2 output fall time (90-10%) t f 10 ns 5, 7 2 single channel product only output enable time to logic high t pzh 30 ns 8 output enable time to logic low t pzl 30 ns 8 output disable time from logic high t phz 45 ns 8 output disable time from logic low t plz 55 ns 8 multi-channel product only input-input insulation leakage current i i-i rh 65%, v i-i = 500 v, t = 5 s 0.5 na 9 resistance (input-input) r i-i v i-i = 500 v 10 13 ? 9 capacitance (input-input) c i-i f = 1 mhz 1.5 pf 9
11 figure 3. output voltage vs. forward input current. figure 4. typical diode input forward characteristic. figure 5. test circuit for t plh , t phl , t r , and t f . gnd v cc i f 5 v d.u.t. 619 ? input monitoring node pulse gen. t r = t f = 5 ns t = 100 khz 10 % duty cycle c l = 15 pf the probe and jig capacitances are included in c l . v o v e output v o monitoring node v cc r f d 1 d 2 5 k d 3 d 4 figure 2. typical logic high output current vs. temperature. figure 1. typical logic low output voltage vs. temperature.
12 figure 8. test circuit for t phz , t pzh , t plz , and t pzl . figure 9. test circuit for common mode transient immunity and typical waveforms. gnd v cc i f +5 v d.u.t. 619 ? pulse generator z o = 50 ? t r = t f = 5 ns c l c l = 15 pf including probe and jig capacitance. v o v e input v o monitoring node v cc d 1 d 2 5 k ? d 3 d 4 s2 s1 v o v ff gnd v cc v cm + pulse gen. a d.u.t. r in v o v e output v o monitoring node v cc 0.1 f bypass b - figure 6. typical propagation delay vs. temperature. figure 7. typical rise, fall time vs. temperature.
13 figure 12. series led drive with open collector gate (4.02 k ? ? ? ? ? resistor shunts i oh from the led). figure 13. recommended lsttl to lsttl circuit. gnd v cc d.u.t. 619 ? v cc1 (+5 v) open collector gate ttl or lsttl data input 4.02 k ? gnd v cc d.u.t. 665 ? v cc1 (+5 v) totem pole output gate ttl or lsttl data input ttl or lsttl data input 665 ? totem pole output gate 1 1 2 0.1 f data output v cc2 (+5 v) data output up to 16 lsttl loads or 4 ttl loads up to 16 lsttl loads or 4 ttl loads figure 10. lsttl to cmos interface circuit. figure 11. recommended led drive circuit. gnd v cc d.u.t. r l 665 ? v cc1 (+5 v) v cc2 (4.5 to 20 v) cmos totem pole output gate v o v e data output ttl or lsttl 2 data input 1 v cc2 5 v 10 v 15 v 20 v r l 1.1 k 2.37 k 3.83 k 5.11 k gnd v cc d.u.t. 750 ? v cc1 (+5 v) totem pole output gate ttl or lsttl data input
www.agilent.com/ semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (408) 654-8675 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/inter- national), or 0120-61-1280(domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2005 agilent technologies, inc. march 8, 2005 5989-2666en mil-prf-38534 class h, class k, and dscc smd test program agilents hi-rel optocouplers are in compliance with mil- prf-38534 classes h and k. class h and class k devices are also in compliance with dscc drawings 5962-88768 and 5962-88769. testing consists of 100% screening and quality conformance inspection to mil-prf-38534. figure 14. single channel operating circuit for burn-in and steady state life tests. gnd v cc v e d.u.t.* *all channels tested simultaneously. conditions: i f = 8 ma v cc + 20 v v in +- i f i o = -14 ma 0.01 f t a = +125 ?c 1.90 v 100 ? i o 1200 ?

▲Up To Search▲

Price & Availability of HCPL-5201

	To Download HCPL-5201 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .